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MM74C373 * MM74C374 3-STATE Octal D-Type Latch * 3-STATE Octal D-Type Flip-Flop
October 1987 Revised May 2002
MM74C373 * MM74C374 3-STATE Octal D-Type Latch * 3-STATE Octal D-Type Flip-Flop
General Description
The MM74C373 and MM74C374 are integrated, complementary MOS (CMOS), 8-bit storage elements with 3STATE outputs. These outputs have been specially designed to drive high capacitive loads, such as one might find when driving a bus, and to have a fan out of 1 when driving standard TTL. When a high logic level is applied to the OUTPUT DISABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74C373 is an 8-bit latch. When LATCH ENABLE is high, the Q outputs will follow the D inputs. When LATCH ENABLE goes low, data at the D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH ENABLE returns high again. The MM74C374 is an 8-bit, D-type, positive-edge triggered flip-flop. Data at the D inputs, meeting the set-up and hold time requirements, is transferred to the Q outputs on positive-going transitions of the CLOCK input. Both the MM74C373 and the MM74C374 are being assembled in 20-pin dual-in-line packages with 0.300" pin centers.
Features
s Wide supply voltage range: s Low power consumption s TTL compatibility: Fan out of 1driving standard TTL s Bus driving capability s 3-STATE outputs s Eight storage elements in one package s Single CLOCK/LATCH ENABLE and OUTPUT DISABLE control inputs s 20-pin dual-in-line package with 0.300" centers takes half the board space of a 24-pin package 3V to 15V s High noise immunity: 0.45 VCC (typ.)
Ordering Code:
Order Number MM74C373M MM74C373N MM74C374M MM74C374N Package Number M20B N20A M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2002 Fairchild Semiconductor Corporation
DS005906
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MM74C373 * MM74C374
Connection Diagrams
MM74C373 MM74C374
Top View
Top View
Truth Tables
MM74C373 Output Disable L L L H
L = LOW logic level H = HIGH logic level X = Irrelevant
MM74C374 D Q Output Disable H L X X H L Q Hi-Z L L L L Clock D Q
LATCH ENABLE H H L X

L H X
H L X X X
H L Q Q Hi-Z
H
= LOW-to-HIGH logic level transition Q = Preexisting output level Hi-Z = High impedance output state
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MM74C373 * MM74C374
Block Diagrams
MM74C373 (1 of 8 Latches)
MM74C374 (1 of 8 Flip-Flops)
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MM74C373 * MM74C374
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin Operating Temperature Range (TA) MM74C373 Storage Temperature Range (TS) Power Dissipation Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Lead Temperature (TL) (Soldering, 10 seconds) 260C 700 mW 500 mW 3V to 15V 18V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
-0.3V to VCC + 0.3V -55C to +125C -65C to +150C
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) IOZ ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE ISOURCE ISINK ISINK Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current 3-STATE Leakage Current Supply Current Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Output Source Current Output Source Current Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V, IO = -10 A VCC = 10V, IO = -10 A VCC = 5V, IO = 10 A VCC = 10V, IO = 10 A VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V, VO = 15V VCC = 15V, VO = 0V VCC = 15V VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = -360 A VCC = 4.75V, IO = -1.6 mA VCC = 4.75V, IO = 1.6 mA VCC = 5V, VOUT = 0V TA = 25C (Note 2) VCC = 10V, VOUT = 0V TA = 25C (Note 2) VCC = 5V, VOUT = VCC TA = 25C (Note 2) VCC = 10V, VOUT = VCC TA = 25C (Note 2) 24 48 mA 6 12 mA -24 -48 mA -12 -24 OUTPUT DRIVE (Short Circuit Current) mA VCC - 0.4 2.4 0.4 VCC - 1.5 0.8 CMOS/LPTTL INTERFACE V V V V V -1.0 -1.0 0.005 -0.005 0.005 -0.005 0.05 300 1.0 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V A A A A Min Typ Max Units
Note 2: These are peak output current capabilities. Continuous output current is rated at 12 mA max.
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MM74C373 * MM74C374
AC Electrical Characteristics
Symbol tpd0, tpd1 Parameter Propagation Delay, LATCH ENABLE to Output
(Note 3)
Conditions Min Typ 165 70 195 85 Max 330 140 390 170 ns Units
MM74C373, TA = 25C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted VCC = 5V, CL = 50 pF VCC = 10V, CL = 50 pF VCC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF tpd0, tpd1 Propagation Delay Data In to Output LATCH ENABLE = VCC VCC = 5V, CL = 50 pF VCC = 10V, CL = 50 pF VCC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF tSET-UP Minimum Set-Up Time Data In to CLOCK/LATCH ENABLE tHOLD = 0 ns VCC = 5V VCC = 10V fMAX Maximum LATCH ENABLE Frequency tPWH Minimum LATCH ENABLE Pulse Width tr, tf t1H, t0H Maximum LATCH ENABLE Rise and Fall Time Propagation Delay OUTPUT DISABLE to High Impedance State (from a Logic Level) tH1, tH0 Propagation Delay OUTPUT DISABLE to Logic Level (from High Impedance State) tTHL, tTLH Transition Time VCC = 5V VCC = 10V VCC 5V VCC = 10V VCC = 5V VCC = 10V RL = 10k, CL = 5 pF VCC = 5V VCC = 10V RL = 10k, CL = 50 pF VCC = 5V VCC = 10V VCC = 5V, CL = 50 pF VCC = 10V, CL = 50 pF VCC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF CLE COD CIN COUT CPD Input Capacitance Input Capacitance Input Capacitance Output Capacitance Power Dissipation Capacitance LE Input (Note 4) OUTPUT DISABLE Input (Note 4) Any Other Input (Note 4) High Impedance State (Note 4) Per Package (Note 5) 200 pF
Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90.
155 70 185 85 70 35 3.5 4.5 6.7 9.0 75 55 NA NA 105 60 105 45 65 35 110 70 7.5 7.5 5 10
310 140 370 170 140 70 ns
ns
MHz 150 110
ns s
210 120 210 90 130 70 220 140 10 10 7.5 15
ns
ns
ns
pF pF pF pF
5
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MM74C373 * MM74C374
AC Electrical Characteristics
Symbol tpd0, tpd1 Parameter Propagation Delay, CLOCK to Output
(Note 6)
Conditions Min Typ 150 65 180 80 70 35 70 50 3.5 5 7.0 10 105 60 105 45 65 35 110 70 15 5 >2000 >2000 7.5 7.5 5 10 250 10 10 7.5 15 210 120 210 90 130 70 220 140 s pF pF pF pF pF ns Max 300 130 360 160 140 70 140 100 ns Units
MM74C374, TA = 25C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted VCC = 5V, CL = 50 pF VCC = 10V, CL = 50 pF VCC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF tSET-UP Minimum Set-Up Time Data In to CLOCK/LATCH ENABLE tPWH, tPWL fMAX t1H, t0H Minimum CLOCK Pulse Width Maximum CLOCK Frequency Propagation Delay OUTPUT DISABLE to High Impedance State (from a Logic Level) tH1, tH0 Propagation Delay OUTPUT DISABLE to Logic Level (from High Impedance State) tTHL, tTLH Transition Time tHOLD = 0 ns VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V VCC = 10V RL = 10k, CL = 50 pF VCC = 5V VCC = 10V RL = 10k, CL = 50 pF VCC = 5V VCC = 10V VCC = 5V, CL = 50 pF VCC = 10V, CL = 50 pF VCC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF tr, tf CCLK COD CIN COUT CPD Maximum CLOCK Rise and Fall Time Input Capacitance Input Capacitance Input Capacitance Output Capacitance Power Dissipation Capacitance VCC = 5V VCC = 10V CLOCK Input (Note 7) OUTPUT DISABLE Input (Note 7) Any Other Input (Note 7) High Impedance State (Note 7) Per Package (Note 8)
Note 6: AC Parameters are guaranteed by DC correlated testing. Note 7: Capacitance is guaranteed by periodic testing. Note 8: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90.
ns ns MHz
ns
ns
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MM74C373 * MM74C374
Typical Performance Characteristics
MM74C373 Propagation Delay, LATCH ENABLE to Output vs Load Capacitance MM74C373, MM74C374 Change in Propagation Delay per pF of Load Capacitance (tPD/pF) vs Power Supply Voltage
MM74C373 Propagation Delay, Data In to Output vs Load Capacitance
MM74C373, MM74C374 Output Sink Current vs VOUT
MM74C373 Propagation Delay, CLOCK to Output vs Load Capacitance
MM74C373, MM74C374 Source Current vs VCC - VOUT
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MM74C373 * MM74C374
Typical Applications
Data Bus Interfacing Element
Simple, Latching, Octal, LED Indicator Driver with Blanking for Use as Data Display, Bus Monitor, P Front Panel Display, Etc.
3-STATE Test Circuits and Switching Time Waveforms
t1H, tH1 t0H , tH0
t1H, CL = 5 pF
t0H, CL = 5 pF
tH1, CL = 50 pF
tH0, CL = 50 pF
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MM74C373 * MM74C374
Switching Time Waveforms
MM74C373
Output Disable = GND
MM74C374
Output Disable = GND
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MM74C373 * MM74C374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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MM74C373 * MM74C374 3-STATE Octal D-Type Latch * 3-STATE Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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